Connect Tech BlueStorm Multi-port Serial Adapter Uživatelský manuál stáhnout pdf (Strana 10)

SPECIAL FEATURE

8 Engineers’ Guide to PCI Express Solutions 2011

Producing the next generation tools for PCI Express Developers feels

like working in the pit for the cyclists in the Tour de France compe-

tition. Over the last few years, test tool requirements have become

more stringent and their necessity to projects has been the diﬀerence

between success and failure. PCI Express is moving in many direc-

tions and it is very challenging to anticipate where it will head next.

PCI Express 3.0 Development

e climb to PCIe 3.0 is in low gear now. Many companies are ﬁnding

themselves ascending steeper development slopes than originally

imagined. Issues such as dynamic equalization and protocol speci-

ﬁcation adherence make this a treacherous path. e PCI Express

3.0 speciﬁcation, ﬁrst announced in 2008, described a new data

rate of 8GT/s and a new encoding format of 128b/130b – all of this

while maintaining backwards compatibility with the legacy Gen1

and Gen2 versions of the same protocol. Dynamic equalization, a

link initialization process where training sequences communicate

transmitter and receiver parameters to establish a link, has been

especially diﬃcult. New structures added to the physical layer, such

as sync header bits, protocol level start tokens for TLPs and DLLPs,

data block streaming and more, require developers to stop and ﬁgure

out how these changes aﬀect their products.

Fixing problems related to this new protocol structure, higher speeds

and dynamic equalization in the pre-silicon period of development is

crucial. One way to insure that this is possible is by having the same

debugging tool and interface for pre-silicon as in the post-silicon

development phase. Many post-silicon tools are more robust and

better suited to interoperability debugging. In some cases, it is even

necessary to combine digital tools with analog tools. For example,

a good way to ﬁnd issues that deal with dynamic equalization are

if both analog waveforms and high level protocol packets are syn-

chronized together with the protocol packet view used to navigate to

hard-to-ﬁnd details of dynamic equalization. Developers seeking to

solve this problem should look to their tool vendor for a full range of

tools that address both the analog and digital layers of the protocol.

What about Gen1 and Gen2?

Although PCI Express 3.0 is the new technology being adopted

by high-performance products such as servers and high-speed

I/O add-in cards, the PCI Express 1.0 and 2.0 technologies are still

moving forward. Over the last several years many applications have

moved from legacy PCI to PCI Express 1.0. is has been true in the

embedded board markets that serve the military, telecommunica-

tions and industrial markets. Standards such as the VITA 46, VITA

42, and AMC.1 R2.0 have started to feature PCI Express I/O. Almost

all new embedded board form factor speciﬁcations announced in the

last few years have PCI Express support on them. VPX backplanes,

AMC, and XMC mezzanine module base applications are moving

from PCIe 1.0 to 2.0. Interoperability between various system com-

ponents is a serious problem that is being addressed through tried

and proven tools coming from the PC/server industry.

One of these embedded technologies that is revolutionizing

embedded platforms is the VPX speciﬁcation – also known as VITA

46 – developed by VITA (VME International Trade Association). It

is a next-generation VMEbus-based system that oﬀers support for

switched fabrics such as PCI Express over a new high-speed con-

nector. Defense and aerospace systems are the primary focus with

a wide range of target applications including graphics, mass storage

and switches.

Debugging embedded systems sometimes presents a probing chal-

lenge to engineers, such as how to take tools used in mainstream

PC/servers and apply them to ﬁx similar issues in the embedded

environment. Test equipment that readily connects to PC or server

boards may not be suitable for a ruggedized backplane. Connectivity

to the device under test must be solved before test equipment can be

deployed to solve problems. Embedded systems engineers depend on

test equipment to be ﬂexible to work in various applications in order

to maximize debugging capability.

“Over the last few years, test tool

requirements have become more

stringent and their necessity to

projects has been the difference

between success and failure.”

This trace of a NVMHCI SSD application taken with the LeCroy Summit

T3-16 Protocol Analyzer shows a decoded SSD NVMHCI 1.0 packet.

PCI Express Climbs to the Top

By John Wiedemeier, LeCroy Corporation

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